1. Field of the Invention
The present invention relates to an operational amplifier and an integrating circuit, in particular an operational amplifier and an integrating circuit having a phase compensation capacitance.
2. Description of Related Art
An integrating circuit to output a signal generated by integrating the current or the voltage of an input signal has been well known. Such an integrating circuit operates by repeating an integration period during which electrical charge is charged to a capacitive element and a reset period during which the electrical charge is discharged from the capacitive element. The signal amplification by the integrating circuit also amplifies an input noise component as well as the input signal component. However, it is possible to reduce the input noise component by lowering the frequency band of the integrating circuit. In order to lower the frequency band of an integrating circuit operating in a predetermined cycle, the reset period needs to be shortened and the integration period needs to be lengthened.
The reset time Trs necessary for the reset action of an integrating circuit using an operational amplifier is determined by the capacitance value Cc of the phase compensation capacitance, the current Ic flowing to the phase compensation capacitance, and the potential difference Vc of the phase compensation capacitance, and expressed as Trs=Vc·Cc/Ic. To shorten this reset period, the current consumption of the operational amplifier needs to be increased or the phase compensation capacitance of the operational amplifier needs to be reduced. Since the phase compensation capacitance has a trade-off relation with the circuit stability of the operational amplifier, in general, the reset period is shortened by increasing the current consumption.
FIG. 6 is the circuit diagram of an integrating circuit shown in FIG. 10 of Japanese Unexamined Patent Application Publication No. 2007-124494. This integrating circuit includes an operational amplifier 17, an input current source 21, a reset switch 19a, and an integrating capacitance 18. The integrating capacitance 18 and the reset switch 19a are connected in parallel between the inverting input terminal and the output terminal 23 of the operational amplifier 17. The integrating capacitance 18 is charged and discharged by the current Iin from the input current source 21, and the voltage integrated by these charge and discharge is output from the output terminal 23 as an output voltage Vout.
FIG. 7 is a timing chart showing the operation of the integrating circuit in FIG. 6. The input current source 21 outputs the current Iin in the positive direction or the negative direction as shown in FIG. 7. The reset switch 19a is a switch to perform a reset action by charging or discharging the integrating capacitance 18 in response to a control signal Prs. It turns on and off by a transfer gate 19 and an inverter 20 at the timing shown in FIG. 7.
The operational amplifier 17 includes a bias circuit 14, a differential amplifier stage 15, and a source-grounded amplifier stage 16. The operational amplifier 17 further includes a phase compensation resistor 5 and a phase compensation capacitance 6 in order to prevent oscillation.
At the bias circuit 14, a constant current is supplied to the P-channel MOSFET 10 by a constant current source 13. A current I1 and a current I4 are supplied to the differential amplifier stage 15 and the source-grounded amplifier stage 16 respectively by a current mirror circuit composed of P-channel MOSFETs 10, 11, and 12.
In the differential amplifier stage 15, a reference voltage Vbias is input to a non-inverting input node 2a, and an input voltage Vin based on the input current Iin is input to an inverting node 1a. Then, differential amplification is performed by a differential pair composed of P-channel MOSFETs 1 and 2 and a current mirror circuit composed of N-channel MOSFETs 3 and 4.
In the source-grounded amplifier stage 16, the drain current of an N-channel MOSFET 7 is changed in accordance with a voltage at a node 9, which serves as the output of the differential amplifier stage 15, and thus the output voltage Vout is changed.
In a period C′ shown in FIG. 7, since the input current previously swings widely in the positive direction, the output voltage Vout of the operational amplifier saturates at a VSS level. In this period, the imaginary short of the differential amplifier stage 15 is collapsed, and the inverting input voltage Vin rises with respect to the non-inverting input voltage Vbias.
Therefore, the gate-source voltage Vgs of the P-channel MOSFET 1 on the inverting input side becomes smaller, and almost no current flows to the P-channel MOSFET 1. That is, the current I2 becomes almost zero, and the current I1 becomes nearly equal to the current I3. Furthermore, almost no current flows to the N-channel MOSFET 4 likewise because of the current mirror circuit composed of the N-channel MOSFETs 3 and 4 of the differential amplifier stage 15. Therefore, the current I3 is supplied to the phase compensation capacitance 6.
The phase compensation capacitance 6 is charged and discharged by the current I3. At this point, since a potential Vco on the output terminal 23 side of the phase compensation capacitance 6 (which is called “output side” hereinafter) is always equal to the output voltage Vout, it is also saturated at the VSS level. Therefore, a potential Vci on the phase compensation resistor 5 side of the phase compensation capacitance 6 (which is called “input side” hereinafter) rises. Specifically, although an equation Vci=Vds(4) holds, the value Vds(4) is not settled in the period C′ as shown in FIG. 7. Then, the potential Vci rises to the level expressed as Vci=VDD−Vds(11)−Vds(2). In these equations, Vds(4) is the drain-source voltage of the N-channel MOSFET 4, Vds(11) is the drain-source voltage of the P-channel MOSFET 11, and Vds(2) is the drain-source voltage of the P-channel MOSFET 2. As a result, since the potential difference Vc of the phase compensation capacitance 6 is expressed as Vc=Vout−Vci, it increases to the minus side.
In a period G′ shown in FIG. 7, since the input current previously swings widely in the negative direction, the output voltage Vout of the operational amplifier saturates at a VDD level. In this period, the imaginary short of the differential amplifier stage 15 is collapsed, and the inverting input voltage Vin falls with respect to the non-inverting input voltage Vbias.
Therefore, the gate-source voltage Vgs of the P-channel MOSFET 1 on the inverting input side becomes larger, and almost the entire current flows to the P-channel MOSFET 1. That is, the current I1 becomes nearly equal to the current I2. Furthermore, substantially the same amount of current as the current I2 flows from the current I4 to the N-channel MOSFET 4 likewise because of the current mirror circuit composed of the N-channel MOSFETs 3 and 4 of the differential amplifier stage 15.
The phase compensation capacitance 6 is charged and discharged by the current I4. At this point, since the output side potential of the phase compensation capacitance 6 is saturated at the VDD level, the input side potential Vci of the phase compensation capacitance 6 falls. Specifically, the potential Vci falls to the level expressed as Vci=Vds(4)≈VSS as shown in FIG. 7. As a result, the potential difference Vc of the phase compensation capacitance 6 increases to the plus side.
The input potentials of the phase compensation capacitance 6 in periods C and G shown in FIG. 7 are determined by the drain-source voltage Vds of the N-channel MOSFET 4. When the differential input of the differential amplifier stage 15 is composed of P-channel MOSFET(s), the potential fluctuations on the input side of the phase compensation capacitance 6 in a saturated state is larger in the period C′ where it swings upward than in the period G′ where it swings downward. Therefore, the time necessary to reset the potential difference Vc of the phase compensation capacitance 6 becomes its maximum in the period C′ where it is saturated at the VSS level. The reset time is determined based on the length of this time.
Since potential difference Vc of the phase compensation capacitance 6 becomes larger when it saturates at the VSS level, the reset time necessary to reset the potential difference Vc in such a state needs to be lengthened. Since the integration period becomes shorter with the increase of the reset time, the frequency band of the integration becomes higher, and thus the noise will increase.
Furthermore, in order to shorten the reset time, the current consumption (I1 and I4) of the operational amplifier needs to be increased or the phase compensation capacitance 6 of the operational amplifier needs to be reduced. Since the circuit stability of the operational amplifier deteriorates with the decrease of the phase compensation capacitance 6, in general, the reset time is shortened by increasing the current consumption. Therefore, the current consumption of the operational amplifier increases.
FIG. 8 is the circuit diagram of an integrating circuit shown in FIG. 1 of Japanese Unexamined Patent Application Publication No. 2007-124494. In contrast to the circuit shown in FIG. 6, it includes a charge/discharge control circuit 25 to control the charge and discharge of the phase compensation capacitance 6 in accordance with a signal Psw, which is in synchronization with the control signal Prs. By connecting one end of the phase compensation capacitance 6 to the VSS and the other end to the reference voltage Vbias, it enables a high-speed reset regardless of the slew rate that is determined within the operational amplifier.
However, the integrating circuit shown in FIG. 1 of Japanese Unexamined Patent Application Publication No. 2007-124494 requires an external high-power current source, and therefore the external circuit becomes larger in scale. Furthermore, there is another problem that the overall current consumption including the current consumption by the external circuit increases.